Owner · alexforencich

alexforencich

alexforencich's tracked open-source repos, sorted by stars.

6 repos

#1
verilog-ethernet ↗@alexforencichVerilog
Verilog Ethernet components for FPGA implementation
★ 3,078+0Star change over the last 7 days
#2
verilog-axi ↗@alexforencichVerilog
Verilog AXI components for FPGA implementation
★ 2,126+0Star change over the last 7 days
#3
verilog-pcie ↗@alexforencichVerilog
Verilog PCI express components
★ 1,655+0Star change over the last 7 days
#4
verilog-axis ↗@alexforencichPython
Verilog AXI stream components for FPGA implementation
★ 913+0Star change over the last 7 days
#5
verilog-i2c ↗@alexforencichVerilog
Verilog I2C interface for FPGA implementation
★ 727+4Star change over the last 7 days
#6
verilog-uart ↗@alexforencichVerilog
Verilog UART
★ 582+0Star change over the last 7 days