pulp-platform

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An open-source microcontroller system based on RISC-V

Common SystemVerilog components

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core