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chipsalliance/verible

@chipsalliance

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Stars
1,927
Forks
303
Language
C++
License
NOASSERTION
Last push
1 week ago
C++lexerhacktoberfestparserproductivityanalysislsp-serverlinterformatterlanguage-server-protocolsyntax-treeyaccsystemverilogstyle-lintersv-lrmsystemverilog-developersystemverilog-parserverible

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