Topic · systemverilog

systemverilog

Tracked open-source repos tagged systemverilog, sorted by stars.

Repos

12

Total stars

13,349

Avg. stars

1,112

Share

0.00%

Topics that frequently appear alongside systemverilog on the same repo.

Recent risers

Repos created in the last 90 days, tagged systemverilog.

No new repos tagged with this topic in the last 90 days.

#1
verible ↗@chipsallianceC++
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
★ 1,927+6Star change over the last 7 days
#2
axi ↗@pulp-platformSystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
★ 1,677+9Star change over the last 7 days
#3
clash-compiler ↗@clash-langHaskell
Haskell to VHDL/Verilog/SystemVerilog compiler
★ 1,609+1Star change over the last 7 days
#4
hdmi ↗@hdl-utilSystemVerilog
Send video/audio over HDMI on an FPGA
★ 1,290+0Star change over the last 7 days
#5
slang ↗@MikePopoloskiC++
SystemVerilog compiler and language services
★ 1,126+2Star change over the last 7 days
#6
kianRiscV ↗@splinedriveVerilog
RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34
★ 1,114+1Star change over the last 7 days
#7
veryl ↗@veryl-langRust
Veryl: A Modern Hardware Description Language
★ 1,029+1Star change over the last 7 days
#8
edalize ↗@olofkPython
An abstraction library for interfacing EDA tools
★ 793+3Star change over the last 7 days
#9
sv2v ↗@zachjsHaskell
SystemVerilog to Verilog conversion
★ 750+1Star change over the last 7 days
#10
vscode-terosHDL ↗@TerosTechnologyVHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
★ 739+0Star change over the last 7 days
#11
core-v-verif ↗@openhwgroupAssembly
Functional verification project for the CORE-V family of RISC-V cores.
★ 717+2Star change over the last 7 days
#12
svls ↗@dalanceRust
SystemVerilog language server
★ 584+1Star change over the last 7 days

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