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Chisel: A Modern Hardware Design Language

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL

Verilator open-source SystemVerilog simulator and lint system

Rocket Chip Generator

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

Scala based HDL

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Modular hardware build system

Veryl: A Modern Hardware Description Language

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

First & Only Text Engine for Unity. Every language. Every emoji. Every style. Production-grade, extensible, high-performance, built on industry standards.Windows, macOS, Linux, Android, iOS, WebGL

⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.

A library which configures a divider for a RecyclerView.