riscv

A simple and easy-to-use library to enjoy videogames programming

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

Tengine is a lite, high performance, modular inference engine for embedded device

Rocket Chip Generator

A fully compliant RISC-V computer made inside the game Terraria

Modern, secure, portable, multiprotocol bootloader and boot manager.

A FPGA friendly 32 bit RISC-V CPU implementation

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

The Ultra-Low Power RISC-V Core

oreboot is a fork of coreboot, with C removed, written in Rust.

MicroPython for K210 RISC-V, let's play with edge AI easier

Unix-like OS in Rust inspired by xv6-riscv

RARS -- RISC-V Assembler and Runtime Simulator

A self-hosting and educational C optimizing compiler

RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see prototyper folder.

The RISC-V Virtual Machine

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The fastest RVA23 RISC-V sandbox

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

3-stage RV32IMACZb* processor with debug

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core