Skip to main content
buildradar
Sign in

darklife/darkriscv

@darklife

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Stars
2,602
Forks
328
Language
Verilog
License
BSD-3-Clause
Last push
2 weeks ago
Verilogrisc-vriscvfpgacoreverilog

No related intel yet

This repo has not appeared in any of the sources the radar tracks. The collector runs on a schedule — check back once it covers this repo.