ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

↗ Open on GitHub

Stars

2,375

Forks

910

Language

Scala

License

BSD-3-Clause

Last push

3 weeks ago

Scala risc-v riscv rtl soc chisel rocket peripherals boom firesim rocket-chip accelerators chip-generator chipyard hwacha out-of-order superscalar

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