soc

One place for all the default credentials to assist the Blue/Red teamers identifying devices with default password 🛡️

A FPGA friendly 32 bit RISC-V CPU implementation

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Open-source AI-powered Security Operations Center — alert fusion, purple-team drills, agent-assisted triage, MITRE ATT&CK investigation. MIT-licensed, self-hostable.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The Ultra-Low Power RISC-V Core

Awesome Security lists for SOC/CERT/CTI

A curated knowledge base to build, run and mature a SOC (including CSIRT).

The SOC Analysts all-in-one CLI tool to automate and speed up workflow.

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

The extensible bootloader for embedded system with application engine, write once, run everywhere.

MasterParser is a powerful DFIR tool designed for analyzing and parsing Linux logs

Tenzir is the data pipeline engine for security teams.

SIEM Tactics, Techiques, and Procedures

Windows应急响应工具---Hawkeye(鹰眼)。集Windows日志分析，进程扫描，主机信息于一体的综合应急响应分析工具

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Awesome list of keywords and artifacts for Threat Hunting sessions

常见的攻击行为监测特征及方法，涵盖端点和流量，未包含PowerShell和Sysmon。预祝运营生活愉快！

Vitis_Accel_Examples

Enterprise-ready SIEM, SOAR and Compliance powered by real-time correlation and threat intelligence.