eugene-tarassov/vivado-risc-v

@eugene-tarassov

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

↗ Open on GitHub

Stars

1,094

Forks

251

Language

Tcl

License

NOASSERTION

Last push

2 months ago

Tcl linux risc-v riscv fpga xilinx vivado boom arty-a7 genesys2 kc705 nexys-video rocketchip vc707

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