syntacore/scr1
@syntacoreSCR1 is a high-quality open-source RISC-V MCU core in Verilog
Stars
1,001
Forks
349
Language
SystemVerilog
License
NOASSERTION
Last push
2 years ago
Related intel (0)
No related intel yet
This repo has not appeared in any of the sources the radar tracks. The collector runs on a schedule — check back once it covers this repo.