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syntacore/scr1

@syntacore

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Stars
1,001
Forks
349
Language
SystemVerilog
License
NOASSERTION
Last push
2 years ago
SystemVerilogrisc-vriscvipcoreverilogrtlrv32erv32emcrv32irv32imc

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