asic

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

SERV - The SErial RISC-V CPU

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Haskell to VHDL/Verilog/SystemVerilog compiler

Berkeley's Spatial Array Generator

Modular hardware build system

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

Digital Signature Service : creation, extension and validation of advanced electronic signatures

VUnit is a unit testing framework for VHDL/SystemVerilog

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ASIC implementation flow infrastructure, successor to OpenLane