olofk/serv

SERV - The SErial RISC-V CPU

↗ Open on GitHub

Stars

1,878

Forks

264

Language

Verilog

License

ISC

Last push

2 weeks ago

Verilog risc-v fpga asic verilog

No related intel yet

This repo has not appeared in any of the sources the radar tracks. The collector runs on a schedule — check back once it covers this repo.