TerosTechnology/vscode-terosHDL

@TerosTechnology

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

↗ Open on GitHub

Stars

738

Forks

71

Language

VHDL

License

GPL-3.0

Last push

1 month ago

VHDL fpga vhdl verilog systemverilog

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