Skip to main content
buildradar
Sign in

zachjs/sv2v

@zachjs

SystemVerilog to Verilog conversion

Stars
750
Forks
66
Language
Haskell
License
BSD-3-Clause
Last push
3 weeks ago
Haskellconversionverilogsystemverilogyosys

No related intel yet

This repo has not appeared in any of the sources the radar tracks. The collector runs on a schedule — check back once it covers this repo.