Owner · chipsalliance

chipsalliance

chipsalliance's tracked open-source repos, sorted by stars.

6 repos

#1
chisel ↗@chipsallianceScala
Chisel: A Modern Hardware Design Language
★ 4,773+9Star change over the last 7 days
#2
rocket-chip ↗@chipsallianceScala
Rocket Chip Generator
★ 3,855+3Star change over the last 7 days
#3
verible ↗@chipsallianceC++
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
★ 1,927+6Star change over the last 7 days
#4
riscv-dv ↗@chipsalliancePython
Random instruction generator for RISC-V processor verification
★ 1,351+1Star change over the last 7 days
#5
Cores-VeeR-EH1 ↗@chipsallianceSystemVerilog
VeeR EH1 core
★ 966+1Star change over the last 7 days
#6
chisel-template ↗@chipsallianceShell
A template project for beginning new Chisel work
★ 708+1Star change over the last 7 days