Topic · asic-design

asic-design

Tracked open-source repos tagged asic-design, sorted by stars.

Repos

4

Total stars

3,443

Avg. stars

861

Share

0.00%

Topics that frequently appear alongside asic-design on the same repo.

Recent risers

Repos created in the last 90 days, tagged asic-design.

No new repos tagged with this topic in the last 90 days.

#1
VeriGPU ↗@hughperkinsSystemVerilog
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
★ 1,367+3Star change over the last 7 days
#2
Cores-VeeR-EH1 ↗@chipsallianceSystemVerilog
VeeR EH1 core
★ 966+2Star change over the last 7 days
#3
qkeras ↗@googlePython
QKeras: a quantization deep learning library for Tensorflow Keras
★ 584+0Star change over the last 7 days
#4
librelane ↗@librelanePython
ASIC implementation flow infrastructure, successor to OpenLane
★ 533+4Star change over the last 7 days

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