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Topic · risc-v

risc-v

Tracked open-source repos tagged risc-v, sorted by stars.

55 repos
  • A hardware-aware guide to data structures for system software engineers.

    1,399+0Star change over the last 7 days
  • A book about how to write OS kernels in Rust easily.

    1,386-1Star change over the last 7 days
  • shecc@sysprog21

    A self-hosting and educational C optimizing compiler

    1,382+1Star change over the last 7 days
  • VeriGPU@hughperkins

    OpenSource GPU, in Verilog, loosely based on RISC-V ISA

    1,367+2Star change over the last 7 days
  • wireguard-fpga@chili-chips-ba

    Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

    1,356+1Star change over the last 7 days
  • RVVM@LekKit

    The RISC-V Virtual Machine

    1,297+0Star change over the last 7 days
  • libriscv@libriscv

    The fastest RVA23 RISC-V sandbox

    1,114+6Star change over the last 7 days
  • :stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers.

    1,109+6Star change over the last 7 days
  • Hazard3@Wren6991

    3-stage RV32IMACZb* processor with debug

    1,105+5Star change over the last 7 days
  • vivado-risc-v@eugene-tarassov

    Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

    1,094+3Star change over the last 7 days
  • firesim@firesim

    FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

    1,039+2Star change over the last 7 days
  • scr1@syntacore

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    1,000+1Star change over the last 7 days
  • Cores-VeeR-EH1@chipsalliance

    VeeR EH1 core

    966+1Star change over the last 7 days
  • weloveinterns@lazyparser

    We ❤️ Interns!

    728+0Star change over the last 7 days
  • core-v-verif@openhwgroup

    Functional verification project for the CORE-V family of RISC-V cores.

    717+2Star change over the last 7 days
  • felix86@OFFTKP

    Run x86 and x86-64 games on RISC‑V Linux

    679+8Star change over the last 7 days
  • RISC-V-Guide@mikeroyal

    RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

    662+2Star change over the last 7 days
  • qtrvsim@cvut

    RISC-V CPU simulator for education purposes

    632+3Star change over the last 7 days
  • DirtyJTAG@dirtyjtag

    JTAG probe firmware

    629+1Star change over the last 7 days
  • rv32emu@sysprog21

    Compact and Efficient RISC-V RV32I[MAFC] emulator

    578+2Star change over the last 7 days
  • bao-hypervisor@bao-project

    Bao, a Lightweight Static Partitioning Hypervisor

    569+6Star change over the last 7 days
  • eclipse-plugins@eclipse-embed-cdt

    The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

    559-1Star change over the last 7 days
  • Projects@MicroCoreLabs

    Ted Fried's MicroCore Labs Projects - FPGA CPU cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8, MCL6809, XTMax, MCL8080+

    529+1Star change over the last 7 days
  • AROS@aros-development-team

    Main AROS repository for active development. Contains the main Operating System components and Build System.

    506+3Star change over the last 7 days
  • RISCBoy@Wren6991

    Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

    506+1Star change over the last 7 days
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